1. Field of the Invention
This invention relates generally to semiconductor fabrication, and more particularly to methods of fabricating stress enhanced transistor devices.
2. Description of Background
Integrated circuits often employ active devices known as transistors such as field effect transistors (FETs). An FET includes a silicon-based substrate comprising a pair of impurity regions, i.e., source and drain junctions, spaced apart by a channel region. A gate conductor is dielectrically spaced above the channel region of the silicon-based substrate. The junctions can comprise dopants which are opposite in type to the dopants residing within the channel region interposed between the junctions. The gate conductor can comprise a doped semiconductive material such as polycrystalline silicon (“polysilicon”). The gate conductor can serve as a mask for the channel region during the implantation of dopants into the adjacent source and drain junctions. An interlevel dielectric can be disposed across the transistors of an integrated circuit to isolate the gate areas and the junctions. Ohmic contacts can be formed through the interlevel dielectric down to the gate areas and/or junctions to couple them to overlying interconnect lines.
Demands for increased performance, functionality, and manufacturing economy for integrated circuits have resulted in extreme integration density and scaling of devices to very small sizes. Transistor device scaling has restricted operating margins and has adversely affected the electrical characteristics of such devices. As such, more emphasis has been placed on achieving higher operating frequencies for transistor devices through the use of stress engineering to improve the carrier mobility of such devices rather than through the use of scaling.
Carrier mobility in the channel of a FET device can be improved by applying mechanical stresses to the channel to induce tensile and/or compressive strain in the channel. The application of such mechanical stresses to the channel can modulate device performance and thus improve the characteristics of the FET device. For example, a process-induced tensile strain in the channel of an n-type (NFET) device can create improved electron mobility, leading to higher saturation currents.
One method used to induce strain in the channel region has been to place a compressively stressed nitride film close to the active region of the FET device. Another approach taken to induce strain in the channel of a p-type (PFET) device has been to epitaxially grow silicon germanium (e-SiGe) in the source and drain regions of the silicon-based substrate. When epitaxially grown on silicon, an unrelaxed SiGe layer can have a lattice constant that conforms to that of the silicon substrate. Upon relaxation (e.g., through a high temperature process) the SiGe lattice constant approaches that of its intrinsic lattice constant, which is larger than that of silicon. Consequently, physical stress due to this mismatch in the lattice constant is applied to the silicon-based channel region.